The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density has generally increased while geometry size has decreased. While these evolution has allowed for increasing production efficiency and lowering associated costs, it has also raised challenges.
For example, in some IC designs it has become desirable conventional polysilicon gate electrode with a metal gate electrode to improve device performance. One process for forming a metal gate structure is referred to as a “gate last” process, where the metal gate structure is fabricated after a sacrificial gate structure is removed from the substrate. For example, in a gate last process, a dummy poly gate is initially formed and the device may continue with processing until deposition of an interlayer dielectric (ILD). The dummy poly gate may then be removed and replaced with a metal gate. This reduces the number of subsequent processes, including high temperature processing, that must be performed after formation of the gate structures. There are challenges to implementing such features and processes however. As the gate length and spacing between devices decreases and loading effect vary (e.g., differing pattern densities), these problems are exacerbated. However, problems arise when integrating the gate last process with other fabrication processes such as chemical mechanical polishing (CMP) of the ILD layer to expose the sacrificial gate for removal. For example, during chemical mechanical polishing (CMP) processes, controlling gate height and/or preventing dishing effects (for example, over-polishing) of an inter-layer dielectric layer may present difficulties. Specifically, CMP processes may result in shorter gate heights, power shorts, and/or high sheet resistances (Rs) of resultant devices. Furthermore, it may be difficult to control a gate height for devices in various regions of the substrate having different pattern densities.
Accordingly, what is needed is a method for fabricating an IC device that addresses the above stated issues.